In contrast to traditional planar metal-oxide-semiconductor field-effect transistors (MOSFETs), which are fabricated using conventional lithographic fabrication methods, nonplanar FETs incorporate various vertical transistor structures, and typically include two or more gate structures formed in parallel. One such semiconductor structure is the “FinFET,” which takes its name from the multiple thin silicon “fins” that are used to form the respective gate channels, and which are typically on the order of tens of nanometers in width.
More particularly, referring to the exemplary prior art nonplanar FET structure shown in FIG. 1, a FinFET 100 generally includes two or more parallel silicon fin structures (or simply “fins”) 104 and 106. These structures are typically formed on a silicon-on-insulator (SOI) substrate (not shown), with fins 104 and 106 extending between a common drain electrode and a common source electrode (not shown). A conductive gate structure 102 “wraps around” three sides of both fins 104 and 106, and is separated from the fins by a standard gate oxide layer 103. Fins 104 and 106 may be suitably doped to produce the desired FET polarity, as is known in the art, such that a gate channel is formed within the near surface of the fins adjacent to gate oxide 103. The width of the gate, indicated by double-headed arrow 108, determines the effective channel length of the device.
The fins historically are fabricated using a procedure that includes the formation of thin sidewall spacers adjacent the sidewalls of larger, sacrificial features called “mandrels.” These spacers are formed by an anisotropic etch of a blanket-coated and conformal, generally dielectric, layer overlying the mandrel. Following formation of the spacers, the sacrificial mandrels are selectively removed leaving the sidewall spacers remaining. These spacers then are used as etch masks for pattern transferring into a silicon-comprising substrate to form fins.
The formation of fins using such spacers presents several shortcomings. Because sidewall spacers are formed by an anisotropic etch along the sidewalls of a substantially straight-walled mandrel, they typically have one substantially straight and vertical sidewall (the surface adjacent the mandrel) and one contoured sidewall (the surface away from the mandrel). The contoured sidewall is typically characterized by a rounded and sloping upper portion that often terminates with a facet and/or a point. The rounded/faceted profile of spacers can be undesirable because the final fin structure may assume a non-rectangular profile or a thinner profile as a result of the pattern transfer process. Because the gate of a FinFET device is also a raised structure that conformably wraps about the fin, such non-rectangular or thinner profile of the fin adversely affects the length and shape of the channel resulting in inconsistent performance in these devices. In addition, such spacers have a high aspect ratio that causes the spacers to have relatively low mechanical stability. Thus, the spacers are prone to breakage, tipping, and collapsing when subjected to mechanical stresses, such as from moving chemicals.
Accordingly, it is desirable to provide methods for fabricating FinFET transistor devices and other semiconductor devices using planarized spacers having a rectangular profile and a reduced aspect ratio that result in improved fin profiles and fewer defects. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description of the invention and the appended claims, taken in conjunction with the accompanying drawings and this background of the invention.